# Control Flow Integrity Design Documentation¶

This page documents the design of the Control Flow Integrity schemes supported by Clang.

## Forward-Edge CFI for Virtual Calls¶

This scheme works by allocating, for each static type used to make a virtual call, a region of read-only storage in the object file holding a bit vector that maps onto to the region of storage used for those virtual tables. Each set bit in the bit vector corresponds to the address point for a virtual table compatible with the static type for which the bit vector is being built.

For example, consider the following three C++ classes:

struct A {
virtual void f1();
virtual void f2();
virtual void f3();
};

struct B : A {
virtual void f1();
virtual void f2();
virtual void f3();
};

struct C : A {
virtual void f1();
virtual void f2();
virtual void f3();
};


The scheme will cause the virtual tables for A, B and C to be laid out consecutively:

Virtual Table Layout for A, B, C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A::offset-to-top &A::rtti &A::f1 &A::f2 &A::f3 B::offset-to-top &B::rtti &B::f1 &B::f2 &B::f3 C::offset-to-top &C::rtti &C::f1 &C::f2 &C::f3

The bit vector for static types A, B and C will look like this:

Bit Vectors for A, B, C
Class 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
A 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0
B 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
C 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Bit vectors are represented in the object file as byte arrays. By loading from indexed offsets into the byte array and applying a mask, a program can test bits from the bit set with a relatively short instruction sequence. Bit vectors may overlap so long as they use different bits. For the full details, see the ByteArrayBuilder class.

In this case, assuming A is laid out at offset 0 in bit 0, B at offset 0 in bit 1 and C at offset 0 in bit 2, the byte array would look like this:

char bits[] = { 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 5, 0, 0 };


To emit a virtual call, the compiler will assemble code that checks that the object’s virtual table pointer is in-bounds and aligned and that the relevant bit is set in the bit vector.

For example on x86 a typical virtual call may look like this:

ca7fbb:       48 8b 0f                mov    (%rdi),%rcx
ca7fbe:       48 8d 15 c3 42 fb 07    lea    0x7fb42c3(%rip),%rdx
ca7fc5:       48 89 c8                mov    %rcx,%rax
ca7fc8:       48 29 d0                sub    %rdx,%rax
ca7fcb:       48 c1 c0 3d             rol    $0x3d,%rax ca7fcf: 48 3d 7f 01 00 00 cmp$0x17f,%rax
ca7fd5:       0f 87 36 05 00 00       ja     ca8511
ca7fdb:       48 8d 15 c0 0b f7 06    lea    0x6f70bc0(%rip),%rdx
ca7fe2:       f6 04 10 10             testb  $0x10,(%rax,%rdx,1) ca7fe6: 0f 84 25 05 00 00 je ca8511 ca7fec: ff 91 98 00 00 00 callq *0x98(%rcx) [...] ca8511: 0f 0b ud2  The compiler relies on co-operation from the linker in order to assemble the bit vectors for the whole program. It currently does this using LLVM’s bit sets mechanism together with link-time optimization. ### Optimizations¶ The scheme as described above is the fully general variant of the scheme. Most of the time we are able to apply one or more of the following optimizations to improve binary size or performance. In fact, if you try the above example with the current version of the compiler, you will probably find that it will not use the described virtual table layout or machine instructions. Some of the optimizations we are about to introduce cause the compiler to use a different layout or a different sequence of machine instructions. #### Stripping Leading/Trailing Zeros in Bit Vectors¶ If a bit vector contains leading or trailing zeros, we can strip them from the vector. The compiler will emit code to check if the pointer is in range of the region covered by ones, and perform the bit vector check using a truncated version of the bit vector. For example, the bit vectors for our example class hierarchy will be emitted like this: Bit Vectors for A, B, C Class 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A 1 0 0 0 0 1 0 0 0 0 1 B 1 C 1 #### Short Inline Bit Vectors¶ If the vector is sufficiently short, we can represent it as an inline constant on x86. This saves us a few instructions when reading the correct element of the bit vector. If the bit vector fits in 32 bits, the code looks like this:  dc2: 48 8b 03 mov (%rbx),%rax dc5: 48 8d 15 14 1e 00 00 lea 0x1e14(%rip),%rdx dcc: 48 89 c1 mov %rax,%rcx dcf: 48 29 d1 sub %rdx,%rcx dd2: 48 c1 c1 3d rol$0x3d,%rcx
dd6:       48 83 f9 03             cmp    $0x3,%rcx dda: 77 2f ja e0b <main+0x9b> ddc: ba 09 00 00 00 mov$0x9,%edx
de1:       0f a3 ca                bt     %ecx,%edx
de4:       73 25                   jae    e0b <main+0x9b>
de6:       48 89 df                mov    %rbx,%rdi
de9:       ff 10                   callq  *(%rax)
[...]
e0b:       0f 0b                   ud2


Or if the bit vector fits in 64 bits:

11a6:       48 8b 03                mov    (%rbx),%rax
11a9:       48 8d 15 d0 28 00 00    lea    0x28d0(%rip),%rdx
11b0:       48 89 c1                mov    %rax,%rcx
11b3:       48 29 d1                sub    %rdx,%rcx
11b6:       48 c1 c1 3d             rol    $0x3d,%rcx 11ba: 48 83 f9 2a cmp$0x2a,%rcx
11be:       77 35                   ja     11f5 <main+0xb5>


#### Padding to Powers of 2¶

Of course, this alignment scheme works best if the address points are in fact aligned correctly. To make this more likely to happen, we insert padding between virtual tables that in many cases aligns address points to a power of 2. Specifically, our padding aligns virtual tables to the next highest power of 2 bytes; because address points for specific base classes normally appear at fixed offsets within the virtual table, this normally has the effect of aligning the address points as well.

This scheme introduces tradeoffs between decreased space overhead for instructions and bit vectors and increased overhead in the form of padding. We therefore limit the amount of padding so that we align to no more than 128 bytes. This number was found experimentally to provide a good tradeoff.

#### Eliminating Bit Vector Checks for All-Ones Bit Vectors¶

If the bit vector is all ones, the bit vector check is redundant; we simply need to check that the address is in range and well aligned. This is more likely to occur if the virtual tables are padded.