User Guide for RISC-V Target¶
Introduction¶
The RISC-V target provides code generation for processors implementing
supported variations of the RISC-V specification. It lives in the
llvm/lib/Target/RISCV directory.
Base ISAs¶
The specification defines four base instruction sets: RV32I, RV32E, RV64I, and RV128I. Currently, LLVM fully supports RV32I, and RV64I. RV32E is supported by the assembly-based tools only. RV128I is not supported.
To specify the target triple:
RISC-V Architectures¶ Architecture
Description
riscv32RISC-V with XLEN=32 (i.e. RV32I or RV32E)
riscv64RISC-V with XLEN=64 (i.e. RV64I)
To select an E variant ISA (e.g. RV32E instead of RV32I), use the base
architecture string (e.g. riscv32) with the extension e.
Extensions¶
The following table provides a status summary for extensions which have been ratified and thus have finalized specifications. When relevant, detailed notes on support follow.
Ratified Extensions by Status¶ Extension
Status
ASupported
CSupported
DSupported
FSupported
HAssembly Support
MSupported
SvinvalAssembly Support
SvnapotAssembly Support
SvpbmtSupported
VSupported
ZbaSupported
ZbbSupported
ZbcSupported
ZbkbSupported (See note)
ZbkcSupported
ZbkxSupported (See note)
ZbsSupported
ZdinxAssembly Support
ZfhSupported
ZfhminSupported
ZfinxAssembly Support
ZhinxAssembly Support
ZhinxminAssembly Support
ZicbomAssembly Support
ZicbopAssembly Support
ZicbozAssembly Support
ZihintpauseAssembly Support
ZknSupported
ZkndSupported (See note)
ZkneSupported (See note)
ZknhSupported (See note)
ZksedSupported (See note)
ZkshSupported (See note)
ZkSupported
ZkrSupported
ZksSupported
ZktSupported
ZmmulSupported
Zve32x(Partially) Supported
Zve32f(Partially) Supported
Zve64xSupported
Zve64fSupported
Zve64dSupported
Zvl32b(Partially) Supported
Zvl64bSupported
Zvl128bSupported
Zvl256bSupported
Zvl512bSupported
Zvl1024bSupported
Zvl2048bSupported
Zvl4096bSupported
Zvl8192bSupported
Zvl16384bSupported
Zvl32768bSupported
Zvl65536bSupported
- Assembly Support
LLVM supports the associated instructions in assembly. All assembly related tools (e.g. assembler, disassembler, llvm-objdump, etc..) are supported. Compiler and linker will accept extension names, and linked binaries will contain appropriate ELF flags and attributes to reflect use of named extension.
- Supported
Fully supported by the compiler. This includes everything in Assembly Support, along with - if relevant - C language intrinsics for the instructions and pattern matching by the compiler to recognize idiomatic patterns which can be lowered to the associated instructions.
Zbkb,ZbkxPattern matching support for these instructions is incomplete.
Zknd,Zkne,Zknh,Zksed,ZkshNo pattern matching exists. As a result, these instructions can only be used from assembler or via intrinsic calls.
Zve32x,Zve32f,Zvl32bLLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result
Zve32xandZve32fare supported only for VLEN>=64. Assembly support doesn’t have this restriction.
Experimental Extensions¶
LLVM supports (to various degrees) a number of experimental extensions. All experimental extensions have experimental- as a prefix. There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised not to make use of experimental extensions before they reach ratification.
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
experimental-zawrsLLVM implements the 1.0-rc3 draft specification. Note that have been backwards incompatible changes made between release candidates for the 1.0 draft.
experimental-zcaLLVM implements the 0.70 draft specification.
experimental-zihintntlLLVM implements the 0.2 draft specification.
experimental-ztsoLLVM implements the v0.1 proposed specification (see Chapter 25). Using will set appropriate ELF flags and attributes, but does not yet change code generation.
experimental-zvfhLLVM implements this draft text.
To use an experimental extension from clang, you must add -menable-experimental-extensions to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM’s internal developer tools (e.g. llc, llvm-objdump, llvm-mc), you must prefix the extension name with experimental-. Note that you don’t need to specify the version with internal tools, and shouldn’t include the experimental- prefix with clang.
Vendor Extensions¶
Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. The term vendor extension roughly parallels the definition of a non-standard extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both custom extensions and non-conforming extensions.
Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the Clang documentation.
It is our intention to follow the naming conventions described in riscv-non-isa/riscv-toolchain-conventions. Exceptions to this naming will need to be strongly motivated.
The current vendor extensions supported are:
XVentanaCondOpsLLVM implements version 1.0.0 of the VTx-family custom instructions specification by Ventana Micro Systems. All instructions are prefixed with vt. as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time.
XTHeadVdotLLVM implements version 1.0.0 of the THeadV-family custom instructions specification by T-HEAD of Alibaba. All instructions are prefixed with th. as described in the specification, and the riscv-toolchain-convention document linked above.
Specification Documents¶
For ratified specifications, please refer to the official RISC-V International page. Make sure to check the wiki for not yet integrated extensions.